The present invention relates to a method of forming a semiconductor device, and more particularly to a method of forming a MOS field effect transistor with gate side wall oxide films.
For high density integration of semiconductor devices, a scaling down of individual elements has progressed. MOS field effect transistors are also required to be scaled down. However, the scaling down of MOS field effect transistors causes short channel effects. It has been proposed to form shallow source/drain diffusion regions so as to suppress the short channel effects. This method of forming the shallow source/drain diffusion regions causes other problems with the increase in sheet resistance and also with the increase in the contact resistance between the diffusion layers and interconnections.
It had also been proposed that in order to solve the above problems, selective growth of silicon films on the source/drain diffusion regions and the gate electrode, along with optional silicidations of the selectively grown silicon films could be made. This method is disclosed in the Japanese laid-open patent publication No. 2-84740. This method allows both the formation of the shallow source/drain diffusion regions and the reduction in contact resistances. This method of forming a MOS field effect transistor will be described with reference to FIGS. 1A through 1D which are fragmentary cross sectional elevation views illustrative of MOS field effect transistors in sequential steps involved in the conventional method.
With reference to FIG. 1A, field oxide films 602 are selectively formed on a top surface of a silicon substrate 601. A gate oxide film 604 is formed on the top surface of the silicon substrate 601. A gate electrode 605 is formed on the gate oxide film 604. Gate side wall silicon oxide films 603 are selectively formed on side walls of the gate electrode 605.
With reference to FIG. 1B, silicon films 606 are selectively grown on the silicon substrate 601 and on the gate electrode 605 Source and drain regions 607 and 608 are then formed.
With reference to FIG. 1C, a titanium film 609 is entirely deposited which extends over the field oxide films 602, the selectively grown silicon films 606 and the gate side wall silicon oxide films 603. The substrate is then subjected to an annealing at a predetermined temperature so as to cause a silicidation reaction of titanium with silicon thereby to selectively form titanium silicide films 610 over the selectively grown silicon films 606 (FIG. 10).
As another conventional method, it had also been proposed that silicon nitride films having a lower etching rate are formed as side walls of the gate oxide films before an epitaxial growth of silicon so as to prevent bottoms of the gate side walls from etching in a process previous to the selective growth of silicon whereby any short circuit formation may be prevented. This conventional method is disclosed in the Japanese laid-open patent publication no. 63-166271.
In the above conventional methods, the silicon films are grown up over the source and drain regions and the gate electrode concurrently. The selective growth process of silicon may, however, have a possibility of undesired deposition of silicon over the insulation films such as the gate side wall insulation films. If the silicon crystal particles are grown on the gate side wall insulation films, then this forms an electrical connection via the silicon crystal particles between the gate electrode and either the source or drain region whereby a short circuit is formed between the gate electrode and either the source or drain region. If particularly thick silicon films are selectively grown, then an effective distance between the gate electrode and either the source or drain region is short. For this reason, small size silicon crystal particle growth on the gate side wall insulation films may form the short circuit. The formation of the short circuit allows a leakage of current between the gate electrode and either the source or drain region.
It had also been proposed to increase the thickness of the gate side wall insulation films in order to avoid the formation of the short circuit between the gate electrode and the either source or drain region. It is however, difficult to form the source and drain regions by ion-implantation through the thick gate side wall insulation films into the silicon substrate. It is possible that the ion is not implanted into the silicon regions under the gate side wall insulation films.
In the above circumstances, it had been required to develop a novel method of forming a MOS field effect transistor with gate side wall insulation films free from the above problems.